1. Technical Field
The embodiments described herein relate to a semiconductor memory device and, more particularly, to a phase change memory device and a method for manufacturing the same.
2. Related Art
A phase change random access memory (PRAM) is a memory device that can be used to stores a set status or a reset status by using resistance differences exhibited from different solid state phases of the phase change material. It should accurately control the resistance of the memory cell. The PRAM includes the contact and the wiring layer for draining the current of the active region to the external of the device in order to control the resistance of the memory cell.
FIG. 1 is a sectional view of a conventional phase change memory device. Referring to FIG. 1, on active regions of a semiconductor substrate 101 which an isolation layer 103 is formed therein, memory cells each including a diode 105, a bottom electrode contact 107 and a phase change pattern 109 are arranged. Top electrode contacts 111 and first conduction patterns 113 are arranged on the phase change patterns 109.
Meanwhile, current control contacts 115 and a second conduction pattern 117 are electrically connected, i.e., coupled, together. The current control contacts 115 and the second conduction pattern 117 drain the current generated in driving the memory cells of the device. The second conduction pattern 117 is configured to be electrically connected to the current control contacts 115.
The phase change memory device should accurately sense a difference in the current across the memory cell as a function of solid state phase the phase change material. However, if the resistance of the active region is greater than a predetermined level, then the PRAM will not be able to adequately sense a current difference between the logic level “0” and the logic level “1” and thereby the PRAM will fail to operate normally.
To protect against encountering this type of problem, the current control contact 115 and the second conduction pattern 117 are introduced to drain the current of the active region away to the outside, as shown in FIG. 1
FIG. 2 is a lay out of the conventional phase change memory device. A plurality of memory cells 120 are arranged in each of a plurality of cell arrays. Core regions are arranged between adjacent cell arrays.
Contact regions 130 which current control contacts 115 are formed therein are arranged at both sides of each of the plurality of cell arrays. Currently, since the current control contacts 115 are repeatedly arranged next to blocks of 8 memory cell units, the size of the chip is increased by about 13%.
Although the current control contacts are used only to drain the current of the active region, current control contacts occupy a considerable portion of the chip size. Furthermore, to form the current control contacts 115, four masks are required to carry out several process steps (up to tens or process steps) using these four masks.
In the prior art phase change memory device, the resistance of the current control contacts is lower than the active region. However, the chip size of the prior art phase change memory device is considerably increased and additional processes are needed to form the current control contacts which thereby lowers the production efficiency.